Power Integrity Lead Engineer @ Intel Technology India

• In this position you will be responsible for providing package and platform power integrity solution for Intel graphics products.
• You will also be required to architect package and board power integrity solution such as voltage rail merging and isolation scheme, stack up and decoupling cap type and to provide design constraints for and guide implementation of component packages and boards to meet design targets.
• You will also be focusing on design processes, techniques including electrical model extraction, development and simulation from Direct Current (DC) to high frequency component on full system power delivery network.
• End goal is to deliver optimized platform electrical solution within the boundary condition followed by design validation and correlation for continuous methodology enhancement.

Your responsibilities will include but not be limited to

• Performs comprehensive simulations and validations to generate Intel design guidelines to guide system level power integrity design including, but not limit to, silicon, package, socket, boards and voltage regulators.
• Performs AC and transient simulation to provide impedance profile of the whole power delivery path, from the VR to the motherboard, the package and the die.
• Provides guidance to the design team on capacitor numbers values and power plane shape width.
• Correlating simulations with system measurements.
• Deliver optimized PI solution meeting the product performance
• Provides DC and resistance simulation to provide Rpath from the VR to the package pins, voltage drop, current density and power loss analysis.
• Performs transfer impedance simulations to provide plane split and isolation guidance between interfaces on board package area.
• As a lead, you will be expected to mentor guide other team members, develop a strong network across organizations and geographies, propose and lead strategic contributions, and role model Intel values.