Job Description: . Minimum 3 years of experience in System Verilog HVL. . Minimum 3 year of experience in OVM/UVM/VMM/Test Harness. . Hands on experience of developing assertion, checkers, coverage and scenario creation. . Must have executed at-least 2 SoC Verification projects . Experience in developing test and coverage plan, Verification environment and validation plan. . Hands on experience on one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required. . Review and Audit participation. . At-least 2 years of experience in handling team of 5 to 10 engineers. . Define/derive Scope, Estimation, Schedule and Deliverables of proposed work.
Employement Category:
Employement Type: Full timeIndustry: ITFunctional Area: ITRole Category: Software EngineerRole/Responsibilies: Technical Lead (Verification)