High Speed IO Logic lead
- Mulya Consulting
- 10 - 16 years
- Bengaluru
- 4 years ago
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Job Description
High Speed IO Logic lead
Top2 Semiconductor Organization in the world
Location: Bangalore
Job Description:
Job Description:
- Energetic and passionate senior Logic Design Engineers to develop high speed Serdes(like PCIe, Ethernet, MIPI CPHY/DPHY/MPHY/APHY etc)
- Person should be able to independently work & develop various logic design and development activities including micro-architecture, RTL code from high level specs, ensure end to end design quality in terms of Lint/CDC/DFT/Synthesis/STA/Formal Equivalence etc.
- Hands on prior experience of developing and working similar high speed Serdes with multiple clock domain, power plan designs
- You would be expected to develop micro-arch of the block/IP you own and also participates in the various Architecture and Microarchitecture specifications forums the Logic components.
- Provides IP integration support to SoC customers and represents RTL/logic design team.
- As design owner, you would also be expected to review and drive test plan, assertions and overall quality of the block/IP.You should be able to interact with various stake holders (internal as well as external) to drive end 2 end quality, design objectives within stipulated schedule timelines.
- Familiarity with overall silicon development cycle from concept to PRQ including DFT/DFD/Post Silicon debug support, HW/SW partitioning is desired.
- Expertise with Verilog, system Verilog, C, C++, Perl languages
- Ability to clearly express technical concepts in verbal and written form
- Innovative thinking, problem solving, good communication skills, self-discipline and results orientation are critical soft-skills needed
- Good hands-on knowledge on industry standard EDA tools & HDLs
- Must be a extremely good team player and should be able to work across organization boundaries and domains
Qualifications:
- Candidate must possess a Bachelor/Master degree in electronics/electrical/communication/VLSI/Microelectronics and/or related engineering/technology with experience of more than 10 years in defining specifications/architecture & execution of RTL/Logic design of IPs in high speed serial IO domain (PCIe, Ethernet, MIPI CPHY/DPHY/MPHY/APHY etc)
Contact: Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : mu**********r@ya**o.com
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area: Engineering - Hardware & Networks, Role Category: HardwareRole: HardwareEmployement Type: Full timeEducation
Under Graduation: B.Tech/B.E. in Any SpecializationPost Graduation: MS/M.Sc(Science) in Any Specialization, M.Tech in Any SpecializationDoctorate: Doctorate Not RequiredContact Details:
Company: Mulya ConsultingLocation(s): Bengaluru
Keyskills: mphy PCIE aphy Logic Design cphy ip integration dphy Serdes Verilog Ethernet System Verilog RTL Design architecture
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