Hi Good day to you.! Openings in Chennai (US based Semiconductor MNC) please go through the Job Descriptions & let me know your interest for the same. Company Name will be Disclosed With your Interest Here attaching the JD for your reference Location :: Chennai Overview:
The candidate will be responsible for synthesis/formal verification and design support for next-generation SoCs subsystems for WIFI/Connectivity chips.
This role will require the candidate to understand and drive Synthesis, Formal verification, and partner with DFT and PD teams for timing convergence.
Synthesis of a subsystem/SOC with multiple Hard Macros
FV with LEC in multiple stages of RTL to NL flow.
Implement the ECO in NL using conformal flow
Work in close coordination with Design, PD, DFT teams to get the goals completed.
Analyze reports/waivers and run various tools: DC, DCT, DCG, Genus, Primetime, etc
Preferred Qualifications:
Synthesis, LEC, low power checks, Memory BIST insertion, SDC validation.
10-15 years of solid experience in synthesis, formal verification with a design background
Expertise in Synopsys DCT/DCG Synthesis/Cadence Genus
Expertise in formal verification with Cadence LEC Understanding of RTL to GDS flow
Expertise in timing closure, PT runs Expertise in Verilog/VHDL Expertise in Perl, TCL language is a plus Expertise in post-Si debug is a plus Good documentation and communication skills.
Note : If you are not Interested, Kindly refer any of your Friends/colleagues with 2+ yrs Thanks & Regards Bala Koppu Technical Recruiter ba*a@ca***o.co.in ,
Employement Category:
Employement Type: Full timeIndustry: Consumer Durables / ElectronicsRole Category: General / Other SoftwareFunctional Area: Not ApplicableRole/Responsibilies: Senior Technical Manager