Physical Design - Lead/Manager
- ACL Digital
- 8 - 13 years
- Bengaluru
- 23 days ago
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Job Description
Job Title: Lead RTL to GDS Engineer Block/Sub-System Level
Company: Wafer Space an ACL Digital Group
Location: Bangalore, India
Experience: 7+ - 20+ Years
Notice Period: Immediate to 30 Days
Compensation: Best in Industry
Overview:
Wafer Space, part of ACL Digital, is actively hiring a Lead RTL to GDS Engineer with deep expertise in block/subsystem-level physical design and signoff for advanced SoC designs (7nm and below). The role involves leading full RTL to GDSII implementation, owning delivery, mentoring junior engineers, and collaborating across functions.
Were looking for professionals who are passionate about driving execution quality, solving complex physical design challenges, and making impactful contributions in high-performance silicon projects.
Key Skills & Responsibilities:
Technical Responsibilities:
- Lead end-to-end RTL to GDSII implementation at block/subsystem level.
- Perform synthesis, floorplanning, placement, CTS, routing, and optimization for PPA.
- Full signoff closure experience including:
- Static Timing Analysis (STA)
- Physical Verification (DRC/LVS using Calibre)
- IR drop, Electromigration (EM), Crosstalk
- Drive low power design closure using UPF/CPF flows.
- Debug and resolve complex design and convergence issues.
- Collaborate with RTL, DFT, verification, and packaging teams for integration and handoff.
- Guide flow/methodology improvements and automation scripting (TCL, Python, Perl).
Leadership Responsibilities:
- Provide technical leadership and mentorship to junior engineers.
- Conduct design reviews and drive quality across the team.
- Interact with program managers and cross-functional teams to ensure timely delivery.
Key Skills:
- RTL to GDSII implementation
- Block & Subsystem level design
- STA (PrimeTime/Tempus)
- Synthesis (Design Compiler/Fusion Compiler)
- Place & Route (ICC2, Innovus)
- Calibre DRC/LVS
- RedHawk / Voltus (IR/EM analysis)
- Low power design (UPF/CPF)
- Scripting (TCL, Python, Perl)
- Tape-out experience at advanced nodes (7nm, 5nm, 3nm)
- Team leadership & technical mentoring
Preferred Experience:
- Experience with TSMC, Samsung, Intel process nodes.
- Hands-on tape-out experience at FinFET nodes (5nm and below).
- Background in SoC integration and hierarchical design.
Why Join Wafer Space an ACL Digital Group?
- Work on cutting-edge SoC designs and the latest technology nodes.
- Be part of a highly technical and collaborative team.
- Best-in-industry compensation and growth opportunities.
- Lead from the front and make a real impact in semiconductor innovation.
If this opportunity isnt for you, please share or refer someone in your network who would be a great fit. Referrals are highly appreciated! (pr*****p@ac*******l.com)
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Physical Design / Layout EngineerEmployement Type: Full timeContact Details:
Company: ACL DigitalLocation(s): Bengaluru
Keyskills: Drc / Lvs Rtl To Gdsii Flow PHYSICAL DESIGN Synthesis Floor Planning STA CTS PNR Placement Cross Talk LVS IR
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