STA Engineer
- Bangalore Labs
- 8 - 13 years
- Bengaluru
- 6 years ago
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Job Description
Job Description Role Responsibilities: Includes definition and development of signoff methodology and corresponding implementation solution. Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/ SoCs. Full chip timing constraints development, full chip / Sub- System STA and Signoff for a complex, multi- clock, multi- voltage SoC. Streamlining the timing signoff criterions, timing analysis methodologies and flows. Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. Work for Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place Route and other local/ remote teams to address the design challenges in the context of the block, chip, and overall system. Concepts of CRPR, clock paths analysis and tweaks to meet timing. Multi Corner and MultiMode analysis. Close timing at SignOff corners covering the entire modes, delay corners for cells and interconnects. Desired Qualification: University degree (B.Tech/ M.Tech) in Electronics/ Electrical Engineering or similar. Other candidates will be considered if they have relevant experience. 3- 7 Years of engineering experience primarily focussing on Physical design. Strong interpersonal skills, excellent verbal and written communication skills. Self- motivated and willing to take up additional responsibilities to contribute to the team s success. Strong analytical, problem solving and debugging skills. Desirable Experience: SoC/ Chip level Timing closure and Signoff of high speed complex design with multiple clocks and power domains with minimal supervision. Working experience on lower technology nodes like 40nm and below till 14nm/ 10nm. Expertise in developing and owning Block and full chip Timing Constraints for complex, multi- clock, multi- voltage SoCs. Expertise in I/ O constraints developments for Industry standard protocols would be an advantage. Good understanding of deep submicron parasitic effects, crosstalk effects, newer statistical timing approaches. Work with the Implementation team in having the SignOff Timing closure done.Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Software & QARole Category: Software DevelopmentRole: Back End DeveloperEmployement Type: Full timeContact Details:
Company: Bangalore LabsLocation(s): Bengaluru+ View Contact
Keyskills: STA ASIC Timing closure Interpersonal skills DFT SOC Mixed signal Analytical Debugging Physical design
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