Physical Design Engineer
- Bangalore Labs
- 3 - 7 years
- Bengaluru
- 6 years ago
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Job Description
Job Description: Role Responsibilities: Responsible for and own all aspects of physical design and physical verification effort at a block level. Worked on Netlist to GDSII at block level for multiple tape- outs. Expertise in hierarchical partitioning of block- level subsystems. Hands on experience in implementing high performance cores, low power designs. Flat timing closure of hierarchical sub systems with signoff STA. Block level floor planning, power planning and IR drop analysis. Formal verification at various levels of design hierarchy with respect to golden RTL. Debugging and solution finding skills. Liaising with Team members and co- workers and Design team for delivery of the project and in finding solution. Develop, support and maintain physical design flows and methodologies. Desired Qualification: University degree (B.Tech/ M.Tech) in Electronics/ Electrical Engineering or similar. Other candidates will be considered if they have relevant experience. 3- 7 Years of engineering experience primarily focussing on Physical design. Strong interpersonal skills, excellent verbal and written communication skills. Self- motivated and willing to take up additional responsibilities to contribute to the team s success. Strong analytical, problem solving and debugging skills. Desirable Experience: Experience in Power, Area with timing closure in parallel. Timing closure with Crosstalk and OCV (Advanced OCV), MMMC optimization. Working experience on various nodes viz. 65nm, 40nm, 28nm, 20nm, 14nm, 10nm. CTS and clock tree constraints creation for meeting clock specifications. Scan chain reordering / Scan Chain repartitioning. Timing ECO and Functional ECO implementation at Netlist stage. Good knowledge of standard cell libraries - circuit design and cell layout. Good understanding of STA, EM / IR and sign- off flows. High Performance Sub- Systems exposure. Understanding of Low Power Design (General Methodology, CPF, UPF). Physical Design Tool expertise viz. Cadence : Encounter / Innovus, Mentor Graphics: Olympus, Synopsys : ICC, ICC2, Atoptech : Aprisa. TCL / PERL Scripting and creating quick procedures for solutions will be a plus. Top level implementation will be an added advantage.Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Software & QARole Category: Software DevelopmentRole: Back End DeveloperEmployement Type: Full timeContact Details:
Company: Bangalore LabsLocation(s): Bengaluru+ View Contact
Keyskills: STA Timing closure formal verification Analytical Debugging Physical verification Perl Mentor graphics Physical design
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