STA / SignOff Timing Closure
- Bangalore Labs
- 3 - 5 years
- Bengaluru
- 5 years ago
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Job Description
STA / SignOff Timing ClosureExperience: 3- 5 Yrs (3 Positions) ASIC/ SoC design implementation experience with specific background in the areas of synthesis, SignOff STA Lower technology nodes like 40nm and below till 14nm/ 10nm. Key Responsibilities: Includes definition and development of signoff methodology and corresponding implementation solution. Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/ SoCs. Full chip timing constraints development, full chip / Sub- System STA and Signoff for a complex, multi- clock, multi- voltage SoC. Streamlining the timing signoff criterions, timing analysis methodologies and flows. Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. Work for Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place Route and other local/ remote teams to address the design challenges in the context of the block, chip, and overall system. Concepts of CRPR, clock paths analysis and tweaks to meet timing. Multi Corner and MultiMode analysis. Close timing at SignOff corners covering the entire modes, delay corners for cells and interconnects.Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Software & QARole Category: Software DevelopmentRole: Technical LeadEmployement Type: Full timeContact Details:
Company: Bangalore LabsLocation(s): Bengaluru+ View Contact
Keyskills: STA ASIC Timing closure git DFT Architecture SOC Mixed signal Manager Technology
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