Asic Dft Engineering Technical Leader @ Cisco

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Qualifications:

• Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience.
• Knowledge of the latest innovative trends in DFT, test and silicon engineering.
• Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

Knowledge of the latest innovative trends in DFT, test and silicon engineering.

• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Prior experience working with Gate level simulation, debugging with VCS and other simulators.
• Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
• Prior experience with Scripting skills: Tcl, Python/Perl.

Preferred Qualifications:

• Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development Test Architecture, Methodology and Infrastructure
• Background in Test Static Timing Analysis
• Past experience with Post silicon validation using DFT patterns.