ASIC Verification Engineer
- Atos
- 3 - 6 years
- Bengaluru
- 1 month ago
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Job Description
Eviden, part of the Atos Group, with an annual revenue of circa ?5 billion is a global leader in data-driven, trusted and sustainable digital transformationAs a next generation digital business with worldwide leading positions in digital, cloud, data, advanced computing and security, it brings deep expertise for all industries in more than 47 countries
By uniting unique high-end technologies across the full digital continuum with 47,000 world-class talents, Eviden expands the possibilities of data and technology, now and for generations to come, Role: ASIC Verification Engineer
Location: Bangalore (Whitefield)
Experience: 3+ years
Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech)
Verificaiton Engineer Integrating ASIC functional verification team
ASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers), Using ?Constraint-Random, Coverage Driven? functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC, Main Responsibilities
Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team, Write and perform the test plan in close cooperation with the logical design team, Develop coverage models and verification environments using UVM-SystemVerilog / C++
Write, maintain and publish the verification specification, Monitor, analyze and debug simulation errors, Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time, Produce a maintainable and reusable code across projects, Skills And Capacities
Curious, demanding and rigorous, Mastering object oriented programming, Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages
Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA)
Knowledge of simulation tools and coverage database visualization tools
Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints
#Eviden
Lets grow together,
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Functional Verification EngineerEmployement Type: Full timeContact Details:
Company: AtosLocation(s): Bengaluru+ View Contact
Keyskills: asic asic verification functional verification system verilogobject oriented programming systemc uvm
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