We are looking for an experienced Physical Design Lead with expertise in Netlist2GDSII implementation, including floor planning, power grid design, CTS, STA, and physical verification. The ideal candidate will have proficiency in Cadence and Synopsys tools and experience with 16nm and below technologies, along with a strong background in SoC integration and low-power/high-speed designs. Leadership in managing teams, handling complex designs, and proficiency in Tcl/Tk/Perl programming is essential, along with excellent communication and customer interaction.
Roles & Responsibilities:
Keyskills: Physical Verification Physical Design Netlist2GDSII Floor Planning Static Timing Analysis Clock Tree Synthesis
At Cyient, we work towards improving the daily lives of people with unwavering focus. From a quieter flight to a safer train journey, a more reliable energy supply, or a faster internet connection, we provide engineering, manufacturing, geospatial, network and operations management services to indus...