SOC Physical design
- IDESLABS
- 3 - 15 years
- Hyderabad
- 2 years ago
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Job Description
- Location: Bangalore, Hyderabad, Noida, and Coimbatore.
- Skills:
- Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration
- Handling timing closure of high frequency blocks.
- Expertise in signoff closure - Timing with SI and OCV, Power, IR and physical verification at both block and chip level.
- Understanding constraints and fixing techniques.
- Experience in physical verification
- Understanding SI prevention, fixing methodology and implementation.
- Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set.
- Experience in Design Automation and UNIX system.
- Experience in Tcl/ PERL is a plus.
- Primary Skills:
- Able to handle Soc PNR activities , SOC timing closure and SOC physical verification
- Secondary Skills:
- Able to handle SOC Synthesis, SOC IR drop, SOC Lec, SOC CLP
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Head - Hardware EngineeringEmployement Type: Full timeContact Details:
Company: IDESLABSLocation(s): Hyderabad
Keyskills: Unix Timing closure Automation SOC Physical verification Mentor Perl Floor planning Budgeting Physical design
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Since its established in August 10 2013 in Hyderabad , Telangana, India, IDESLABS Pvt Ltd has committed to provide high quality of Consulting Services and Corporate Trainings to our customers in locally in India and across the globe. With our TEAM’s passion towards the o...
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