Design Verification Engineering Manager
- Meta
- 12 - 17 years
- Bengaluru
- 18 hours ago
- Email to a friend
- Report this job
Job Description
Apply to this job Lead an Application-Specific Integrated Circuit (ASIC) design verification team, including managers responsible for various processing blocks within a System-on-Chip (SOC). Manage the development and execution of verification plans, drive innovative verification methodologies, and ensure both functional and code coverage closure. Collaborate closely with Architecture, Software/Firmware, Design, Modeling, Emulation, and Post-Silicon Validation teams to support silicon architecture and micro-architecture development, ensuring seamless integration and successful project outcomes.
Design Verification Engineering Manager Responsibilities
- Collaborate with cross-functional teams, including executives, managers, and individual contributors (development engineers, capacity planners, supply chain experts) to drive business objectives.
- Develop and maintain the overall silicon strategy aligned with the corporations Long Range Plan objectives.
- Partner with IP development teams to identify, select, and license soft and hard IP.
- Lead a team of ASIC engineers through hiring, training, and guidance to ensure on-time and on-budget product delivery.
- Analyze and review SOWs from vendors, supporting documentation, and requirements sets to meet internal customer needs.
- Support engineering teams in defining, debugging, implementing, and delivering total solutions around purpose-built ASICs.
- Establish and maintain key performance indicators (KPI) for areas of responsibility.
- Partner with technical program management and supply chain teams to manage external development partners, suppliers, and vendors.
- Provide support to design verification team managers.
Minimum Qualifications
- B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a relevant technical field (or equivalent practical experience)
- 12+ years of ASIC/SoC design verification experience
- 7+ years of people management experience, including leading managers and experienced Individual contributors
- In depth understanding of design verification tools such as Synopsys VCS, Cadence Xcelium Simulator, Verdi, JasperGold, or VC Formal
- Proven track record of first-pass success in ASIC development
- Experience managing multiple projects, prioritizing tasks, and collaborating with stakeholders
- Skilled in Universal Verification Methodology (UVM) constrained random test bench development and delivery
- Capacity to interpret functional specs and create comprehensive test plans
- Experience managing managers who support small to mid-sized teams
Preferred Qualifications
- In-depth knowledge of at least one area: Video coding standards, Signal processing algorithms, Neural networks and machine learning concepts, Other neural network development frameworks, Experience with formal verification techniques and methodologies
- Hands-on experience with complex subsystems, including memory Low Power Double Data Rate, High Bandwidth Memory, cache, Peripheral Component Interconnect Express, and network-on-chip, with a focus on performance verification
About Meta
.
Equal Employment Opportunity
.
Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .
Job Classification
Industry: InternetFunctional Area / Department: Engineering - Hardware & NetworksRole Category: HardwareRole: Design Verification EngineerEmployement Type: Full timeContact Details:
Company: MetaLocation(s): Bengaluru+ View Contact
Keyskills: Supply chain ASIC Coding SOC Debugging Machine learning Signal processing Firmware UVM silicon validation
Fraud Alert to job seekers!
₹ Not Disclosed
Similar positions
Job Listings
We are in open beta version of website, please let us know if any issues, at: info(at)indigojobs.in