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Physical Design Engineer @ Intel

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 Physical Design Engineer

Job Description


 Job Details: 
 : 
  • Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
  • Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  • Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  • Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
  • Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
  • Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
  • Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

    •  Qualifications: 
    Qualifications:
  • B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects.
  • Has good understanding on timing methodology, constraints building etc.
  • Experience in floorplaning concepts and actual work, and integration of hierarchical design
  • Good understanding and experience with multiple power domains designs.
  • Have hands on experience on LV flow and clean up.
    •  Job Type: Experienced Hire
     Shift: Shift 1 (India)
     Primary Location: India, Bangalore
     Additional Locations: 
     Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.
     Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
      
     Position of Trust N/AWork Model for this Role
    This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

    Job Classification

    Industry: Electronic Components / Semiconductors
    Functional Area / Department: Engineering - Hardware & Networks
    Role Category: Hardware
    Role: ASIC / RTL / Logic Design Engineer
    Employement Type: Full time

    Contact Details:

    Company: Intel
    Location(s): Bengaluru

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    Keyskills:   physical design static timing analysis synthesis floor planning timing closure floorplan route3 routing drc perl tcl sta eda primetime lvs rtl timing analysis cadence verilog dft pnr placement synopsys power integrity clock tree synthesis

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