RTL Lead Engineer
- TekWissen
- 6 - 9 years
- Mysuru
- 30 days ago
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Job Description
Overview:
TekWissen is a global workforce management provider throughout India and many other countries in the world.
Position: RTL Lead Engineer
Location: Mysore
Work Type: Onsite
Job Type: Full time
Job Description:
- Strong proficiency in Verilog and SystemVerilog, with experience in designing finite state machines (FSMs), clocking, reset strategies, and bus architectures.
- Capable of developing microarchitecture from specification to RTL, including block and subsystem design, as well as thorough documentation.
- Skilled in RTL debugging, with working knowledge of synthesis processes and timing closure.
- Familiar with industry protocols and integration, such as AXI, APB, AHB, PCIe, SoC integration, design-for-test (DFT), and power domain management.
Good to Have Skills:
- Experience with scripting and automation using Python, Tcl, or Perl to streamline design flows.
- Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, AMS integration, UPF-based low-power design, post-silicon debugging, and a proactive approach to automation
TekWissen Group is an equal opportunity employer supporting workforce diversity.
Job Classification
Industry: Electronic Components / SemiconductorsFunctional Area / Department: Research & DevelopmentRole Category: Engineering & ManufacturingRole: Design EngineerEmployement Type: Full timeContact Details:
Company: TekWissenLocation(s): Mysuru+ View Contact
Keyskills: Perl TCL Python SystemVerilog RTL Coding RTL Design
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