Skills requried:
In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes.
- Should have experience in Analog and Mixed Signal Design
Should have experience in handling >5M instance count , 1.5GHz frequency designs.
Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.
Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2)
Strong experience on Static Timing Analysis (PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).
Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improvements.
Experience in complex SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.
Keyskills: physical design static timing analysis soc icc ems finishing routing ic design design perl tcl sta mixed signal cts primetime timing ir analysis cadence physical verification analog floor planning pnr grid tk mixed signal design synopsys soc integration power integrity
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