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DV Engineer -GLS @ TekWissen

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 DV Engineer -GLS

Job Description

Overview: 

TekWissen is a global workforce management provider throughout India and many other countries in the world. 


Position: DV Engineer -GLS

Location: Bangalore

Work Type: Onsite
Job Type: Full time


Job Description:


Key Responsibilities:

  • Develop and implement scalable UVM-based verification environments
  • Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role
  • Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies
  • Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure
  • Analyze waveforms, root-cause issues, and contribute to debugging complex logic

Requirements:
Required Skills:

  • Solid hands-on experience with SystemVerilog and UVM methodologies
  • Strong understanding and application of GLS (Gate-Level Simulation) techniques
  • Experience with CDC verification and asynchronous domain handling
  • Familiarity with tools such as VCS, Questa, Incisive
  • Scripting knowledge (Python, Perl, or Shell) is a plus

TekWissen Group is an equal opportunity employer supporting workforce diversity.

Job Classification

Industry: Electronic Components / Semiconductors
Functional Area / Department: Research & Development
Role Category: Engineering & Manufacturing
Role: Design Engineer
Employement Type: Full time

Contact Details:

Company: TekWissen
Location(s): Bengaluru

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Keyskills:   Gls SystemVerilog Design Verification Verilog UVM

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