Summary of Role :
Receive input from our IP design groups and use it to compose customer collateral documents (e.g., spec sheets, databooks, application notes).
IP types include Standard Cell Logic libraries, eFuse, and IO libraries in various technology nodes.
Essential Responsibilities :
Compose high quality customer collateral for use by our customers to determine whether our IP can suit their needs and how to make use of our IP in their designs.
All current documentation is created using FRAMEMAKER. Suitable candidates should have prior experience with the use of this tool or should be able to show, from previous job experience, the ability to learn/adapt to different documentation tools.
Having a technical background that would allow the candidate to critique input being provided by the design teams is a very strong plus.
Required Qualifications :
Education: BS 5 years experience, or MS 3 years experience in Electrical or Computer Engineering
Minimum of 3 - 5 years of experience with digital/analog IP circuit design, layout, and timing experience
Language Fluency - Fluent in English Language - written verbal.
Fluency in documentation tools, like FRAMEMAKER and WORD
Must be able to interpret electrical design specifications
Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary
Candidates who are self-driven and have worked in a global team environment with a successful track record of on-time high quality IP design creation.
Be able to collaborate with program and technical design leads on multiple concurrent projects.
Should have excellent problem solving skills, written oral communication, teaming interpersonal skills
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety Security requirements and programs
Preferred Qualifications:
Having a technical background that would allow the candidate to critique input being provided by the design teams is a very strong plus.
Knowledge of the end-to-end IP and Chip design cycles is desirable
Knowledge in RF technologies (Bulk, CMOS SOI) is desirable.
Project management, Schedule development, SOW creation skills are desirable.
Keyskills: Electrical design RF Chip design Technical writing Project management Analog Circuit designing SOW Documentation tools