Hi Good day to you.! Openings with US based Semiconductor MNCs please go through the Job Descriptions & let me know your interest for the same. Company/ies Name will be Disclosed With your Interest Work Location : Bangalore & Hyderabad Here attaching the JD for your reference Responsibilities:
Design DFT logic including inserting MEMBIST, boundary scan, scan, and at speed ATPG (Transition Delay Fault Testing).
Work with digital design and backend teams on DFT architecture/partitioning.
Run RTL, gate, and gate with SDF simulations to confirm correct functionality of DFT logic.
Generate ATPG vectors, bring-up and debug patterns, resolve test pattern and coverage issues, support test engineering and operations through qualification, burn-in, and production
Support failure analysis and fault isolation of pattern failures
Qualifications:
Must have experience inserting, testing, and using DFT logic functions (JTAG, BIST, mBIST, scan, boundary scan, ATPG) on multiple chips that have been through tape-out and product ramp.
Must have experience with logic design, especially involving multiple clock domains.
Must have some experience with Perl or other similar scripting languages.
Experience with silicon lab bring-up.
Experience operating a tester to debug patterns is a plus.
Experience with physical design tools (such as PrimeTime) is a plus.
Must be able to work within a small team on multiple tasks.
Clear written and verbal communication skills
Education and Experience:
BS (MS preferred) in Electrical Engineering, Computer Science, or related field
Minimum 3+ years applicable experience
Note : If you are not Interested, Kindly refer any of your Friends/colleagues with 3+ yrs Thanks & Regards Bala Koppu Technical Recruiter ba*a@ca***o.co.in ,
Employement Category:
Employement Type: Full timeIndustry: Consumer Durables / ElectronicsRole Category: General / Other SoftwareFunctional Area: Not ApplicableRole/Responsibilies: R&D Senior Engineer/ Manager/ Senior